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| Data Sheet, V1.7, July 2003 HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/L3.6] HYB25D128323C[-4.5/L4.5] HYB25D128323C-5 128 Mbit DDR SGRAM Memory Products Never stop thinking. Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, V1.7, July 2003 HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/L3.6] HYB25D128323C[-4.5/L4.5] HYB25D128323C-5 128 Mbit DDR SGRAM Memory Products Never stop thinking. HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/L3.6], HYB25D128323C[-4.5/L4.5], HYB25D128323C-5 Revision History: Previous Version: Page all 43 46 48 9, 13, 42, 46, 48 V1.7 V1.51 2003-07 2002-07 Subjects (major changes since last revision) new data sheet template AC Operation Conditions: Input Slew Rate added Timing Parameters for speed sorts -3, -3.3, -3.6, -4.5, and -5: Write DQS High/Low added Timing Parameters for speed sorts L3.6 and L4.5: Write DQS High/Low added V1.51 2002-07 extended VDD range for -3.6 and L3.6 Previous Version: We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.0_2003-06-06.fm HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.3.1 3.4 3.4.1 3.4.2 3.4.3 3.4.3.1 3.4.3.2 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.10 3.5.11 3.5.12 3.5.13 3.5.14 3.5.15 3.5.16 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 3.8 3.9 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Setup (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal and Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Inputs and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Strobe and Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation at Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation at Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Activation Command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Read Operation: (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Write Operation (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Stop Command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Mask (DMx) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autoprecharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Autoprecharge (READA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge (WRITEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 16 16 17 17 17 17 17 18 20 20 20 20 21 21 22 23 23 24 24 25 26 27 28 28 30 31 31 32 33 33 34 34 35 36 41 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet 5 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Ball Out 128Mbit DDR SGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command and Address Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DQS Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DQS and DM Timing at Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DQS Pre/Postamble at Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activate to Read or Write Command Timing (one bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activate Bank A to Activate Bank B Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autorefresh timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Stop for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Mask Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Burst with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Burst with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read interrupted by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write interrupted by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 15 16 17 18 19 19 20 20 21 21 22 23 23 24 25 26 27 28 29 30 31 32 32 33 33 34 35 41 43 52 Data Sheet 6 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Data Sheet 7 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signal and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IO Driver Strength and Interface Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mapping of DQSx and DMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Precharge Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst Mode and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Concurrent Read Auto Precharge Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Concurrent Write Auto Precharge Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Timing Parameters for speed sorts -3, -3.3, -3.6, -4.5, and -5 . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Parameters for speed sorts L3.6 and L4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 HYB25D128323C-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HYB25D128323C-3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HYB25D128323C-3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HYB25D128323C-4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HYB25D128323C-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HYB25D128323CL3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 HYB25D128323CL4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Data Sheet 8 V1.7, 2003-07 128 Mbit DDR SGRAM HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/L3.6] HYB25D128323C[-4.5/L4.5] HYB25D128323C-5 1 1.1 * * * * * * * * * * * * * * * * * * * * * * Overview Features Maximum clock frequency up to 333 MHz Maximum data rate up to 666 Mbps/pin Data transfer on both edges of clock Programmable CAS latency of 2, 3 and 4 clocks Programmable burst length of 2, 4 and 8 Integrated DLL to align DQS and DQ transitions with CLK Data transfer signals are synchronized with byte wise bidirectional Data Strobe Data Strobe signal edge-aligned with data for Read operations Data Strobe signal center aligned with data for Write operations Differential clock inputs (CLK and CLK) Data mask for masking write data, one DM per byte Organization 1024K x 32 x 4 banks 4096 rows and 256 columns per bank 4K Refresh (32ms) Refresh Interval 7.8 sec Autorefresh and Self Refresh available Standard JEDEC TF-XBGA 128 package Self-mirrored, symmetrical ball out Matched Impedance Mode interface (Z0=60) SSTL-2 JEDEC Weak Mode interface (Z0=34) IO voltage VDDQ = 2.5 V VDD power supply memory core: - Speed sorts -3 and -3.3: 2.5 V < VDD < 2.9 V - Speed sorts L4.5, -4.5, and -5: VDD = 2.5 V - Speed sorts L3.6 and -3.6 support both VDD modes Performance -3 -3.3 3.3 300 4.0 250 1.15 0.30 -3.6 3.6 278 4.2 238 1.26 0.33 -4.5 4.5 222 4.5 222 1.58 0.45 -5.0 5.0 200 5.0 200 1.75 0.5 L3.6 3.6 278 4.2 238 1.26 0.33 L4.5 4.5 222 4.5 222 1.58 0.45 Unit ns MHz ns MHz ns ns Table 1 Part Number Speed Code CAS Latency 4 CAS Latency 3 Data Out Window DQS-DQ Skew tCK4min. fCK4max. tCK3min. fCK3max. tQH tDQSQ 3 333 4.0 250 1.05 0.30 1.2 Description The Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all requirements for high bandwidth intensive applications like PC graphics systems. The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks x 4096 rows x 256 columns x 32 bits. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single Read or Write access to the DDR Data Sheet 9 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Overview SGRAM consists of a single 64-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32-bit wide, one-half clock cycle data transfers at the I/O pins. The result is a data rate of 666 Mbits / sec per pin. The external data interface is 32 bit wide and achieves at 333 MHz system clock a peak bandwidth of 2.66 Gigabytes/sec. The device is supplied with 2.5 V resp. within the range of 2.5 V - 2.9 V for the memory core and 2.5 V for the output drivers. Two drivers strengths are available: 2.5 V Matched Impedance Mode and SSTL2 Weak Mode. The "Matched Impedance Mode" interface is optimized for high frequency digital data transfers and matches the impedance of graphics board systems (60Ohm). Auto Refresh and Self Refresh operations are both supported. A standard JEDEC TF-XBGA 128 package is used which enables ultra high speed clock and data transfer rates. The signals are mapped symmetrically to the balls in order to enable mirrored mounting in application. The chip is fabricated in Infineon technologies advanced 256M process technology. Data Sheet 10 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Pin Configuration 2 Pin Configuration 1 A B C D E F G H J K L M DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 2 DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 3 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 4 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 5 DQ2 DQ1 VSSQ VSSQ 6 DQ0 VDDQ VDD VSS 7 DQ31 VDDQ VDD VSS 8 DQ29 DQ30 VSSQ VSSQ 9 DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ 10 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CLK A8/AP 11 DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CLK# CKE 12 DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF TOP VIEW 128 BALL XBGA 4 Banks x 4096 Rows x 256 Columns x 32 Bits VSS A10 A2 A1 VSS VDD A11 A3 VSS VDD A9 A4 VSS RFU A5 A6 VSSQ VSS RFU A7 CAS# WE# RAS# CS# NC NC Figure 1 Ball Out 128Mbit DDR SGRAM Note: The inner matrix of 4 x 4 balls will be used as thermal VSS contacts ncluding the thermal VSS contacts, the total amount of balls is 144 Data Sheet 11 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Pin Configuration Table 2 Pin CLK, CLK Signal and Pin Description IO Type Detailed Function Input Clock: CLK and CLK# are differential clock inputs. All address and command inputs are latched on the crossing of the positive edge of CLK and the negative edge of CLK. Output data (DQ's and DQS) is referenced to the crossing of CLK and CLK. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWERDOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row active in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF-REFRESH exit. CKE must be maintained HIGH trough out READ and WRITE accesses. Input buffers (excluding CLK, CLK) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: CS# enables the command decoder when low and disables it when high. When the command decoder is disabled, new commands are ignored, but internal operations continue. CS# is considered part of the command code. Command Inputs: CAS, RAS, and WE (along with CS) define the command to be executed. Bank Address Inputs: BA0 and BA1 select to which internal bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. They also define which mode register (mode register or extended mode register) is loaded during a MODE REGISTER SET command. Address Inputs: During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11). During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA7). In addition to the column address, A8/AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A8 is high, the active bank is precharged. If A8 is low, the Autoprecharge function is disabled. During a Precharge command cycle, A8/AP is used to determine, which bank(s) will be precharged. If A8/AP is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A8/AP is low, BA0 and BA1 define the bank to be precharged. The address inputs also provide the op-code during a MODE REGISTER SET command. Data Strobes: The DQSx are the bidirectional strobe signals. At read cycles, the DQSx signals are generated by the SGRAM and are edge-aligned to the data. At write cycles, the DQS signals are generated by the controller. The rising or falling edge indicates the center of the data valid window. Before and after a transfer cycle, DQSx enters a preamble and a postamble state. The DQSx signals are mapped to the following data bytes: DQS0 to DQ0.. DQ7, DQS1 to DQ8.. DQ15, DQS2 to DQ16..DQ23, DQS3 to DQ24.. DQ31. Data Input/Output: The DQx signals form the 32 bit wide data bus. At READ cycles the pins are outputs and during WRITE cycles inputs. The data is transferred at both edges of the DQSx signals. CKE Input CS Input RAS, CAS, WE Input BA1, BA0 Input A11.. A0 Input DQS3.. DQS0 I/O DQ31.. DQ0 I/O Data Sheet 12 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Pin Configuration Table 2 Pin DM3.. DM0 Signal and Pin Description (cont'd) IO Type Detailed Function Input Input Data Mask: The DM signals are input mask signal for WRITE data. They mask off a complete byte on the data bus. DMx = 1 prevents the corresponding byte from being written. DM3 corresponds to DQ31..DQ24, DM2 to DQ23..DQ16, DM1 to DQ15..DQ8, DM0 to DQ7..DQ0. DM signals are sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Voltage Reference: VREF is the reference voltage input signal. Power Supply: Power and Ground for the internal logic. VDD = 2.5 V 5% for L4.5, -4.5, and -5 2.5 V - 5% < VDD < 2.9 V for -3.6 and L3.6 2.5 V < VDD < 2.9 V for -3 and -3.3 IO Power Supply: Isolated Power and Ground for the output buffers to provide improved noise immunity. VDDQ = 2.5V 5% Please do not connect No Connect, Reserved for Future Use pins. Must be connected to low VREF VDD, VSS Input Supply VDDQ, VSSQ NC, RFU MCL Supply - - Data Sheet 13 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Pin Configuration Column Addresses A7-A0, AP Column Address Buffer Column Address Counter Row Addresses A11-A0, BA1-BA0 Row Address Buffer Refresh Counter Sense Amplifiers and Data Bus Buffer Row Decoder Column Decoder Memory Array Bank 3 4096 x 256 x 32 bit Control Logic & Timing Generator CLK CLK# CKE CS# RAS# CAS# WE# Vref Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer Column Decoder Column Decoder Bank 0 Bank 1 Column Decoder Memory Array Memory Array Sense Amplifiers and Data Bus Buffer Row Decoder Row Decoder Row Decoder Memory Array Bank 2 4096 x 256 x 32 bit 4096 x 256 x 32 bit 4096 x 256 x 32 bit Input Buffers Output Buffers DQ31-DQ24 DQ23-DQ16 DQ15-DQ8 DQ7-DQ0 DQS3 DQS2 DQS1 Data Data Data Data DM3 DM2 DM1 DQS0 Figure 2 Functional blocks Data Sheet 14 DM0 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3 3.1 Register Set Mode Register The mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The default value of the mode register is not defined. Therefore the mode register must be written after power up to operate the DDR SGRAM. The DDR SGRAM should be activated with CKE already high prior to writing into the Mode Register. The Mode Register is written by using the MRS command. The state of the address signals registered in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS latency (read latency from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7, A8 and BA1 must be set to low for normal DDR SGRAM operation. A9.. A11 is reserved for future use. BA0 selects Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 RFU RFU RFU DLL TM CAS Latency BT Burst Length Mode Register Extended Mode Register Access BA0 0 1 Accessed Register Mode Register Extend. Mode Reg. Testmode A7 0 1 mode Normal Testmode Burst Type A3 0 1 Type Sequential Reserved DLL Reset A8 0 1 DLL Reset No Yes CAS Latency A6 0 0 1 A5 1 1 0 A4 0 1 0 Latency 2 3 4 All other Reserved Burst Length A2 A1 A0 Length Sequential 2 4 8 Interleave 2 4 8 0 0 0 0 1 1 1 0 1 All other Reserved Figure 3 Mode Register Bitmap Data Sheet 15 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.2 Extended Mode Register Setup (EMRS) The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed by performing a normal Mode Register Setup operation and setting the BA0 bit to high. All other bits of the EMRS register are reserved and should be set to low. The Bit A0 enables / disables the DLL. The Bits A1 and A6 set the driver strength of the IOs. For detailed explanation, refer to the following table. Table 3 A6 0 0 1 1 IO Driver Strength and Interface Settings A1 0 1 0 1 Drive Strength SSTL-2 weak SSTL-2 weak RFU matched impedance mode Strength/ Impedance 60% / 34Ohm 60% / 34Ohm RFU 30% / 60Ohm IO Power Supply VDDQ 2.5V 2.5V RFU 2.5V Comment replacement for strong mode - Do not use output driver matches line impedance Note: The combination A6=0 and A1=0 defines SSTL-2 strong mode in 32M DDR SGRAM which is not supported in this device. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 1 RFU must be set to "0" DS1 RFU must be set to "0" DS0 DLL Extended Mode Register Extended Mode Register Access BA0 0 1 Accessed Register Mode Register Extend. Mode Reg. A6 0 0 1 1 A1 0 1 0 1 Drive Strength SSTL II-Weak Mode SSTL II-Weak Mode RFU Matched Impedance 2.5V A0 0 1 DLL Enable Enable Disable Figure 4 Extended Mode Register Bitmap 3.3 3.3.1 Signal and Timing Description General Description The 128Mbit DDR SGRAM is a 16MByte Synchronous Graphics DRAM. It consists of four banks. Each bank is organized as 4096 rows x 256 columns x 32 bits. Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address bits registered coincident with the Activate command are used to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A11.. A0 select the row. Address bits A7.. A0 registered coincident with the Read or Write command are used to select the starting column location for the burst access. The regular Single Data Rate SGRAM read and write cycles only use the rising edge of the external clock input. For the DDR SGRAM, the special signals DQSx (Data Strobe) are used to mark the data valid window. During Data Sheet 16 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set read bursts, the data valid window coincides with the high or low level of the DQSx signals. During write bursts, the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge of DQSx, therefore the data transfer rate is doubled. For Read accesses, the DQSx signals are aligned to the clock signal CLK. 3.4 3.4.1 Special Signal Description Clock Signal The DDR SGRAM operates with a differential clock (CLK and CLK#) input. CLK is used to latch the address and command signals. Data input and DMx signals are latched with DQSx. The DDR SGRAM implements a Delay Locked Loop circuit (DLL) which tracks both edges of the CLK input signal and aligns the DQS output edges with the CLK input edges. The minimum and maximum clock cycle time is defined by tCK. The maximum value for tCK is defined to provide a lower bound for the operation frequency of the internal DLL circuit. The minimum and maximum clock duty cycle are specified using the minimum clock high time tCH and the minimum clock low time tCL respectively. The internal DLL circuit requires additional 200 clock cycles after DLL reset for internal clock stabilization. 3.4.2 Command Inputs and Addresses Like single data rate SGRAMs, each combination of RAS#, CAS# and WE# input in conjunction with CS# input at a rising edge of the clock determines a DDR SGRAM command. VIH CLK, CLK# VIL tIS Address, CS#, RAS#, CAS#, WE#, CKE Valid tIH Valid VIH VTT VIL Figure 5 Command and Address Signal Timing 3.4.3 3.4.3.1 Data Strobe and Data Mask Operation at Burst Reads The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The data strobe signal goes tRPRE clock cycle low before data is driven by the DDR SGRAM and then toggles low to high and high to low till the end of the burst. The CAS latency is specified to the first low to high transition. The edges of the Output Data signals and the edges of the data strobe signals during a read are nominally coincident with edges of the input clock. The tolerance of these edges is specified by the parameters tAC and tDQSCK and is referenced to the crossing point of the CLK and CLK# signal. The tDQSQ timing parameter describes the skew between the data strobe edge and the output data edge. The following table summarizes the mapping of DQSx and DMx signals to the data bus. Data Sheet 17 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 4 Mapping of DQSx and DMx data mask signal DM0 DM1 DM2 DM3 Controlled data bus DQ7 .. DQ0 DQ8 .. DQ15 DQ16 .. DQ23 DQ24 .. DQ31 data strobe signal DQS0 DQS1 DQS2 DQS3 The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define the minimum output data valid window. Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit from Hi-Z to a valid logic low. This is referred to as the data strobe "read preamble" tRPRE. Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe "read postamble" tRPST. T0 CLK, CLK# tCH tCL T1 tCK T2 tHP T3 T4 VIH VIL tDQSCK "Preamble" tRPRE "Postamble" tRPST DQS VIH VTT VIL tAC DQx tDQSQ D tQH D+1 D+2 D+3 VIH VTT VIL tQHS Figure 6 DQS Timing for Read 3.4.3.2 Operation at Burst Write During a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the setup and hold time parameters of data (tQDQSS & tQDQSH) and data mask (tDMDQSS & tDMDQSH). The input data is masked in the same cycle when the corresponding DMx signal is high (i.e. the DMx mask to write latency is zero.) Data Sheet 18 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set DQSx VIH VTT VIL tDMDQSS tDMDQSS VIH VTT VIL DMx tDMDQSH tQDQSH tQDQSH Q+1 Q+2 tQDQSS Input Data masked Q+3 tDMDQSH DQx Q tQDQSS Q+4 VIH VTT VIL Figure 7 DQS and DM Timing at Write Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal (DQSx) transits from Hi-Z to a valid logic low. This is referred to as the data strobe "Write Preamble". Once the burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal (DQSx) transits from a valid logic low to Hi-Z. This is referred to as the data strobe "Write Postamble", tWPST. For DDR SGRAM, data is written with a delay which is defined by the parameter tDQSS (DDR write latency). This is different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued. CLK, CLK# VIH VIL WR tDQSS tWPREH DQSx tWPRES "Preamble" "Postamble" tWPST VIH VTT VIL DQx Q Q+1 Q+2 Q+3 VIH VTT VIL Figure 8 DQS Pre/Postamble at Write Data Sheet 19 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.5 3.5.1 Description of Timings Power-Up Sequence The following sequence is highly recommended for Power-Up: 1. Apply power and start clock. Maintain CKE=L and the other pins are in NOP conditions at the input 2. Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF & VTT 3. Start clock, maintain stable conditions for 200 s min. 4. Apply NOP and set CKE to high 5. Apply a Precharge All command 6. Issue EMRS (extended mode register set) command to enable the DLL 7. Issue a Mode Register Set command for "DLL reset". 200 cycles of clock input are required to lock the DLL. 8. Issue Precharge commands for all banks of the device. 9. Issue two or more Auto-Refresh commands. 10. Issue a Mode Register Set command. (This step may also be taken as step 6) Clock any Comm. Command NOP PREA EMRS DLL Reset PREA ARef ARef MRS tRP tMRD 2 Clock min. tRP tRFC tRFC tMRD 200 Clock min. Figure 9 Power-Up Sequence 3.5.2 Mode Register Set Timing The DDR SGRAM should be activated with CKE already high prior to writing into the mode register. Two clock cycles are required to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. Clk any Comm. Command NOP PREA NOP MRS NOP NOP tRP tMRD Figure 10 Mode Register Set Timing 3.5.3 Extended Mode Register Set Timing The timing of the Extended Mode Register Setup operation is equivalent to the Mode Register Setup timing. Data Sheet 20 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.5.4 Bank Activation Command (ACT) The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR SGRAM has four independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank Activation command must be applied before any Read or Write operation can be executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCDDC min. for read commands and tRCDWR min. for write commands). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank activation delay time (tRRD min). Clk Command ACT READ or WRITE PRE NOP ACT tRCDRD for read tRCDWR for write Addresses Bank A Row Add. Bank A Col. Add. Bank A Bank A Row Add. tRC Figure 11 Activate to Read or Write Command Timing (one bank) Clk Command ACT NOP ACT Addresses Bank B Row Add. Bank A Row Add. tRRD Figure 12 Activate Bank A to Activate Bank B Timing 3.5.5 Precharge Command This command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be precharged. After a Precharge command, the analog delay tRP has to be met until a new Activate command can be initiated to the same bank. Data Sheet 21 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 5 A8/AP 0 0 0 0 1 Precharge Control BA1 0 0 1 1 X BA0 0 1 0 1 X Precharged Bank A Only Bank B Only Bank C Only Bank D Only All Banks Clk Command ACT NOP PRE NOP ACT Addresses Bank A Row Add Bank A Bank A Row Add tRAS tRC tRP Figure 13 Precharge Command Timing 3.5.6 Self Refresh The self refresh mode can be used to retain the data in the DDR SGRAM if the chip is powered down. To set the DDR SGRAM into a self refreshing mode, a Self Refresh command must be issued and CKE held low at the rising edge of the clock. Once the self Refresh command is initiated, CKE must stay low to keep the device in Self Refresh mode. During the Self refresh mode, all of the external control signals are disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL before returning CKE high. After the Power Down Exit time(tPDEX), a Deselect or NOP command is issued and CKE is held high for longer than tSREX in order to lock the DLL. Data Sheet 22 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Clk Command NOP SELF REFRESH NOP DESEL NOP DESEL NOP DESEL NOP DESEL Any Comm. CKE tSREX Figure 14 Self Refresh timing 3.5.7 Auto Refresh The auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks must be precharged and idle before the Auto Refresh command is applied. No control of the external address pins is required once this cycle has started. All necessary addresses are generated in the device itself. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC(min). Clk Command NOP PRECHARGE AUTO REFRESH Command NOP CKE Command is AUTOREFRESH or ACT tRP tRFC Figure 15 Autorefresh timing 3.5.8 Power Down Mode The Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is sampled at the rising edge of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except CLK, CKE and DLL circuits are gated off to reduce power consumption. All banks can be set to idle state or stay activate during Power Down Mode, but burst activity may not be performed. After exiting from Power Down Mode, at least one clock cycle of command delay must be inserted before starting a new command. During Power Down Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer than the refresh period (tREF) of the device. Data Sheet 23 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Clk Command PRE NOP NOP NOP DESEL Any Command NOP DESEL CKE Power Down Mode entry Power Down Mode exit tPDEX Figure 16 Power Down Mode timing 3.5.9 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory (read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup command. The burst length controls the number of words that will be output after a read command or the number of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2, 4 or 8 data words. Table 6 Burst Mode and Sequence Starting Column Address A2 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Access within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Burst Length 3.5.10 Burst Read Operation: (READ) The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after tRCD from the bank activation. The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2, 4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on the CAS latency. The subsequent data is clocked out on the rising and falling edge of DQSx until the burst is completed. The DQSx signal is generated by the DDR SGRAM during Burst Read Operations. Data Sheet 24 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK Command Read NOP CL = 2 NOP NOP NOP NOP NOP NOP Read Postamble DQSx CAS latency = 2 DQx D-out 0 CL = 3 D-out 1 D-out 2 D-out 3 Burst length = 4 Read Preamble Read Postamble Read Preamble DQSx CAS latency = 3 DQx D-out 0 D-out 1 D-out 2 D-out 3 CL = 4 Read Postamble Read Preamble DQSx CAS latency = 4 DQx D-out 0 D-out 1 D-out 2 D-out 3 Figure 17 Burst Read Operation 3.5.11 Burst Write Operation (WRITE) The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A7.. A0) determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the first rising edge of DQSx following the WRITE command. The time between the WRITE command and the first corresponding edge of the data strobe is tDQSS. The remaining data inputs must be supplied on each subsequent rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Data Sheet 25 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK WRITE tDQSS DQSx tWPRES NOP NOP tWPST NOP tWPREH DQx Data-in 0 Data-in 1 Data-in 2 Data-in 3 Burst length = 4 Figure 18 Burst Write Operation 3.5.12 Burst Stop Command (BST) A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has been completed. When the Burst Stop Command is issued during a burst read cycle, read data and DQSx go to a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation. Burst Stop is also illegal during Read with Auto-Precharge. Data Sheet 26 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK Command READ CL = 2 BST NOP NOP NOP NOP NOP NOP Burst Stop Latency = 2 DQSx CAS latency = 2 DQx CL = 3 Burst Stop Latency = 3 DQSx CAS latency = 3 DQx D-out 0 D-out 1 D-out 0 D-out 1 Burst Stop Latency = 4 DQSx CAS latency = 4 DQx D-out 0 D-out 1 Burst length = 4 Figure 19 Burst Stop for Read 3.5.13 Data Mask (DMx) Function The DDR SGRAM has a Data Mask function that can be used only during write cycles. When the Data Mask is activated (DMx high) during burst write, the write operation is masked immediately. The DMx to data-mask latency is zero. DMx can be issued at the rising or falling edge of Data Strobe. Data Sheet 27 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK Command WRITE NOP NOP NOP NOP NOP NOP NOP DQSx DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-in 6 D-in 7 DMx Data is masked out Burst length = 8 Figure 20 Data Mask Timing 3.5.14 Autoprecharge Operation The Autoprecharge command is issued by setting column address A8 high when a Read or a Write command is asserted to the DDR SGRAM. If A8 is low when Read or Write command is issued, a normal Read or Write burst operation is executed and the bank remains active at the end of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle after tRAS(min.) is satisfied. 3.5.15 Read with Autoprecharge (READA) If a Read with Auto-precharge command is initiated, the DDR SGRAM automatically enters the precharge operation BL/2 clock cycles after the READA command and tRAS(min.) is satisfied. If tRAS(min.) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (tRP) has been satisfied. Data Sheet 28 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK Command READA NOP NOP NOP NOP NOP NOP ACT CL = 2 DQSx CAS latency = 2 DQx D-out 0 CL = 3 D-out 1 D-out 2 D-out 3 DQSx CAS latency = 3 DQx D-out 0 CL = 4 D-out 1 D-out 2 D-out 3 DQSx CAS latency = 4 DQx BL / 2 D-out 0 D-out 1 t RP D-out 2 D-out 3 Burst length = 4 Begin of Autoprecharge Bank can be activated after completion of precharge Figure 21 Read Burst with Autoprecharge Data Sheet 29 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Burst length = 4 T0 CLK T1 CAS latency = 3 T2 T3 T4 T5 T6 T7 T8 Command BANK A ACTIVATE NOP NOP t RCD(min) t RAS(min) READ A + AP NOP NOP NOP NOP NOP t RP BL / 2 Begin of Auto Precharge DQSx CL = 3 DQx D-out 0 D-out 1 D-out 2 D-out 3 Figure 22 Table 7 Asserted Command READ READ+AP ACTIVATE Read Concurrent Auto Precharge Concurrent Read Auto Precharge Support For same Bank T4 NO YES NO YES T5 NO YES NO YES T6 NO NO NO NO For different Bank T4 NO NO YES YES T5 YES YES YES YES T6 YES YES YES YES PRECHARGE Note: This table is for the case of Burst Length = 4, CAS Latency =3 and tWR=2 clocks When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in Table 7. An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another READ+AP command is allowed, it will extend the begin of the internal Precharge operation to the last READ+AP command. Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent command to another active bank. ACTIVATE or PRECHARGE commands to another bank are always possible while a READ with Auto Precharge operation is in progress. 3.5.16 Write with Autoprecharge (WRITEA) If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal precharge begins after the write recovery time tWR and tRAS(min.) are satisfied. If a Write with Auto Precharge command is initiated, the DDR SGRAM automatically enters the precharge operation at the first rising edge of CLK after the last valid edge of DQS (completion of the burst) plus the write recovery time tWR. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (tRP) has been satisfied. If tRAS(min.) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied. Data Sheet 30 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command BANK A ACTIVATE NOP WRITE A + AP NOP NOP NOP NOP NOP NOP t RAS(min) t WR t RP BL / 2 Begin of Auto Precharge DQSx DQx D-in 0 D-in 1 D-in 2 D-in 3 Figure 23 Write Burst with Auto Precharge Note: tWR starts at the first rising edge of clock after the last valid edge of the 4 DQSx. Table 8 Asserted Command WRITE WRITE+AP READ READ+AP ACTIVATE PRECHARGE Concurrent Write Auto Precharge Support For same Bank T3 NO YES NO NO NO NO T4 NO NO NO NO NO NO T5 NO NO NO NO NO NO T6 NO NO NO NO NO NO T7 NO NO NO NO NO NO T8 NO NO NO NO NO NO For different Bank T3 NO NO NO NO YES YES T4 YES YES NO NO YES YES T5 YES YES NO NO YES YES T6 YES YES NO NO YES YES T7 YES YES YES YES YES YES When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in Table 8. An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP command is allowed as long as the burst is running, it will extend the begin of the internal Precharge operation to the last WRITE+AP command. Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent WRITE's to another active bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are possible. ACTIVATE or PRECHARGE commands to another bank are always possible while a WRITE with Auto Precharge operation is in progress. 3.6 3.6.1 Burst Interruption Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by a new Read command given to any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the Data Sheet 31 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval (CAS#(a) to CAS#(b) Command period, tCCD) is minimum 1 CLK. CLK Command READ a tCCD READ b NOP NOP NOP NOP DQSx DQx D-out a0 D-out a1 D-out b0 D-out b1 D-out b2 D-out b3 Burst length = 4 CL = 2 Figure 24 Read interrupted by Read 3.6.2 Read Interrupted by a Write To interrupt a burst read with a write command, a Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's (Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated (Last Output to Write Command Latency). To insure that the DQs are tri-stated one cycle before the write operation begins, the Burst Stop command must be applied at least 3 clock cycles for CL = 2, at least 4 clock cycles for CL = 3 or at least 5 clock cycles for CL = 4 before the Write command. CLK Command READ BST NOP Burst Stop latency = CL NOP WRITE NOP NOP NOP DQSx DQx D-out 0 D-out 1 D-in 0 D-in 1 D-in 2 D-in 3 Burst length = 4 CL = 2 Burst Stop to Write command latency Figure 25 Read interrupted by Write Data Sheet 32 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.6.3 Read Interrupted by a Precharge A Burst Read operation can be interrupted by a Precharge of the same bank. The Read command to Precharge time is minimum 1 clock cycle. The Precharge command disables the data output depending on the CAS latency. Once the last data bit has been outputted, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. CLK Command READ NOP PRE NOP Precharge latency = CL NOP ACT NOP First possible ACT command DQSx DQx D-out 0 D-out 1 D-out 2 D-out 3 tRP Burst length = 8 CL = 2 Figure 26 Read interrupted by Precharge 3.6.4 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write Command. The minimum distance between two different Write commands is one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. The Write to Write interval (CAS a to CAS b command period) is defined by the parameter tCCD. CLK Command WRITE a tCCD WRITE b NOP NOP NOP DQSx DQx D-in a0 D-in a1 D-in b0 D-in b1 D-in b2 D-in b3 Burst length = 4 Figure 27 Write interrupted by Write Data Sheet 33 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.6.5 Write Interrupted by a Read A Burst Write can be interrupted by a Read command sent to any bank. The DQs must be in the high impedance state at least one clock cycle before the data of the interrupting read appears on the outputs to avoid data contention. Before the Read Command is registered, any residual data from the burst write cycle must be masked by DMx. Data that is presented on the DQ pins before the Read command is initiated, will actually be written to the memory. CLK Command Write tDQSS NOP NOP Last valid data tWTR Read NOP CL = 2 NOP NOP DQSx DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-out 0 D-out 1 DMx Data must be masked Data is masked by Read Burst length = 8 CL = 2 Figure 28 Write interrupted by Read 3.6.6 Write Interrupted by a Precharge A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank. Random column access is allowed. A Write Recovery time (tWR) is required from the last data to Precharge command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DMx. Data Sheet 34 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set CLK Command Write bank A tDQSS NOP NOP Last valid data NOP tWR PRE Write bank B tDQSS NOP NOP DQSx DQx D-in 0 D-in 1 D-in 2 D-in 3 D-in 4 D-in 5 D-in 0 D-in 1 DMx Data must be masked Data is masked by Precharge Burst length = 8 Figure 29 Write interrupted by Precharge 3.7 Table 9 Operation Operations and Functions Command Overview Code DESEL NOP MRS CKE n-1 H H H H H H H H H H H H H H L L CKE n X X X X X X X X X X X X H L H H CS# H L L L L L L L L L L L L L H L RAS# CAS# WE# X H L L L L H L H H L L L L X H X H L L H H L H L H H H L L X H X H L L H H H H H L L L H H X H BA0 X X 0 1 BA BA BA BA BA X BA X X X X X BA1 X X 0 0 BA BA BA BA BA X BA X X X X X A8 X X A0-7 A9-11 X X Device Deselect No Operation Mode Register Setup OPCODE OPCODE Row Address L H L H X L H X X X X Col. Col. Col. Col. X X X X X X X Extended Mode Register MRS Setup Bank Activate Read Read with Auto Precharge Write Command Write Command with Auto Precharge Burst Stop Precharge Single Bank Precharge All Banks Auto Refresh Self Refresh Entry Self Refresh Exit ACT READ READA WRITE WRITEA BST PRE PREAL AREF SREFEN SREFEX Data Sheet 35 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 9 Operation Command Overview (cont'd) Code CKE n-1 H H L CKE n L L H CS# H L H L RAS# CAS# WE# X H X valid X H X valid X H X valid BA0 X X X BA1 X X X A8 X X X A0-7 A9-11 X X X Power Down Mode Entry PWDNEN (Note) Power Down Mode Exit PWDNEX Note: The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations. 3.8 Function Truth Tables Table 10 lists all abbreviations used in Table 11 and Table 12. Table 10 H L X V RA BA PA NOP CA Ax Table 11 IDLE Abbreviations High Level Low Level Don't Care Valid Data Input Row Address Bank Address Precharge All No Operation Column Address Address Line x Function Truth Table I Command DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Address X X X BA,CA,A8 BA,CA,A8 BA, RA BA, A8 X Op-Code Action NOP NOP NOP ILLEGAL ILLEGAL Bank Active NOP AUTO-Refresh or Self-Refresh Mode Register Set or Extended Mode Register Set 4)5) Current State Notes 3)1) 3)2) 3) 1)4) 1) 3) 3) 1) 1) 4) Data Sheet 36 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 11 Function Truth Table I (cont'd) Command DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS READ DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS READ with DESEL Auto Precharge NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS WRITE DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Address X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X Op-Code X X BA BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code Action NOP NOP NOP Begin Read, Determine Auto Precharge Begin Write, Determine Auto Precharge ILLEGAL Precharge / Precharge All ILLEGAL ILLEGAL Continue burst to end Continue burst to end Terminate Burst Terminate burst, Begin New Read, Determine Auto-Prechgarge ILLEGAL ILLEGAL Terminate Burst / Precharge ILLEGAL ILLEGAL Continue burst to end, Precharge Continue burst to end, Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Terminate Burst, Begin Read, Determine Auto-Precharge. Terminate Burst, Begin new Write, Determine Auto-Precharge ILLEGAL Terminate Burst , Precharge ILLEGAL ILLEGAL 7), 8) 1) 1) 7)8) 9)6) 9) Current State ROW ACTIVE Notes 9) 1), 5) 9) 6) 1), 5) 6)7) 7) 2), 7) 2), 7)9) 1) 1) 1) 1) 7), 8) 2), 7) 2), 7) 1) 8) 1) 8) Data Sheet 37 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 11 Function Truth Table I (cont'd) Command DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS ROW ACTIVATING DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS PRECHARGE DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS WRITE DESEL RECOVERING NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS Address X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code Action Continue burst to end, Precharge Continue burst to end, Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP ( Row Active after tRCD) NOP ( Row Active after tRCD) NOP ( Row Active after tRCD) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP ( Row Idle after tRP) NOP ( Row Idle after tRP) NOP ( Row Idle after tRP) ILLEGAL ILLEGAL ILLEGAL NOP ( Row Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tWR) NOP (Row Active after tWR) NOP (Row Active after tWR) Begin Read, Determine Auto-Prechgarge Begin Write, Determine Auto-Prechgarge ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2) 2) 1) 1) 1) 1) 1), 9) 1), 9) 1), 5) 1), 6) 1) 1) Current State WRITE with Autoprecharge Notes 1) 1) 1), 9) 1), 9) 1), 5) 1), 6) 1) 1) 1) 1) 2) 2) 1),10) Data Sheet 38 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 11 Function Truth Table I (cont'd) Command Address X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA ,A8 X OP-Code Action NOP (Precharge after tWR) NOP (Precharge after tWR) NOP (Precharge after tWR) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after two clocks) NOP (Idle after two clocks) NOP (Idle after two clocks) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 11) 1), 2) 1) 1) 1) Current State Notes DESEL WRITE RECOVERING NOP with AutoBST precharge READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS REFRESH DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS (EXTENDED MODE REGISTER SET) DESEL NOP BST READ / READA WRITE / WRITEA ACT PRE / PREAL AREF / SREF MRS / EMRS 1) Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank 2) Must satisfy bus contention, bus turn around, write recovery requirements. 3) If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and CLK# will be disabled. 4) If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter SelfRefresh Mode. All input buffers except CKE will be disabled. 5) Illegal, if tRRD is not satisfied. 6) Illegal, if tRAS is not satisfied. 7) Must satisfy burst interrupt condition. 8) Must mask two preceding data bits with the DM pin. 9) Illegal, if tRCD is not satisfied. 10) Illegal, if tWR is not satisfied. 11) Illegal, if tRC is not satisfied. Note: All entries assume the CKE was High during the preceding clock cycle Data Sheet 39 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set Table 12 Current State SELF REFRESH Function Truth Table for CKE CKE n-1 H L L L L L L CKE n X H H H H H L X H L H L L L L L L X H CS# X H L L L L X X X X X L H L L L L X X RAS # X X H H H L X X X X X L X H H H L X X CAS # X X H H H L X X X X X L X H H L X X X WE# X X H X X X X X X X X H X H L X X X X Address Action X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh ( Idle after tSRX) Exit Self-Refresh ( Idle after tSRX) ILLEGAL ILLEGAL ILLEGAL NOP ( Maintain Self Refresh) INVALID Exit Power Down ( Idle after tPDEX) NOP ( Maintain Power Down) Refer to Function Truth Table Enter Self Refresh Enter Power-Down Enter Power-Down ILLEGAL ILLEGAL ILLEGAL Refer to Power Down in this table Refer to Funtion Truth Table 2) 3) 2) 2) 2) 2) 2) Notes 1) 1) 1) 1) 1) 1) 1) POWER DOWN H L L H H H H H H H L ALL BANKS IDLE All other states H 1) CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any commands other than EXIT are executed. 2) Power Down can be entered when all banks are idle (banks can be active or precharged) 3) Self Refresh can be entered only from the Precharge / Idle state. Data Sheet 40 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Register Set 3.9 DDR SGRAM Simplified State Diagram SELF REFRESH SREFEN SREFEX MODE REGISTER SET MRS IDLE AUTO REFRESH CKEL ACT CKEH CKEH CKEL POWER AREF DOWN ROW ACTIVE WRITE WRITEA READ READA READ BST WRITE READ READA WRITEA READA PRE PRE PRE WRITEA READA POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence Figure 30 DDR SGRAM Simplified State Diagram Data Sheet 41 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics 4 Table 13 Parameter Electrical Characteristics Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1.4 50 max. -0.5 -0.5 -0.5 -0.5 0 -55 - - Unit Note/ Test Condition - - - - - - - - Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT VDDQ + V 0.5 +3.6 +3.6 +3.6 +70 +150 - - V V V C C W mA Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 14 Parameter Power Supply Voltage Power & DC Operation Conditions Symbol min. VDD VDD VDD VDD Power Supply Voltage for I/O Buffer Reference Voltage Termination Voltage Input leakage current CLK Input leakage current Output leakage current Input logic high voltage, DC Input logic low voltage, DC VDDQ VREF VTt IIL IILC IOL VIH VIL 2.38 2.38 2.5 2.5 2.38 0.49 x VDDQ VREF - 0.04 -5 -5 -5 VSSQ - 0.3 Values typ. max. 2.5 2.5 -- -- 2.5 2.63 2.63 2.9 2.9 2.63 V V V V V V L3.6, L4.52) -3.6, -4.5, -5 2) -3.6, L3.6 2)3) -3, -3.3 2) 2) 4) 5) 6) Unit Notes 1) 1.25 0.51 x VDDQ -- -- -- -- 5 5 5 VDDQ + 0.3 VREF - 0.15 VREF VREF + 0.04 V A A A V V 7) -- -- -- 8) 9) VREF + 0.15 -- Output Levels: Matched Impedance Mode 2.5V High Current at VOUT = VDDQ-0,373V Low Current at VOUT = 0.373V Output Levels: SSTL2 Weak Mode 2.5V High Current at VOUT = VDDQ - 0,373V Low Current at VOUT = 0.373V IOH IOL -5 5 -- -- -- -- mA mA -- -- IOH IOL -5 5 -- -- -- -- mA mA -- -- Data Sheet 42 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics 1) TA = 0 to 70 C; VSS = 0 V 2) Under all conditions, VDDQ must be less than or equal to VDD 3) The speed sorts L3.6 and -3.6 support both VDD modes: 2.5V 5% and 2.5V - 2.9V 4) VDDQ = 2.5 V -/+5% 5) Typically the value of VREF is expected to be 0.5 * VDDQ of the transmitting device. VREF is expected to track variations in VDDQ 6) Peak to peak AC noise on VREF may not exceed 2% VREF (DC) 7) VTT of the transmitting device must track VREF of the receiving device 8) Overshoots of VIH must be limited to a voltage < (VDDQ + 1.5 V) and a pulse width < 0.33 of the clock pulse 9) Undershoots of VIL must be limited to a voltage > -1.5 V and a pulse width < 0.33 of the clock pulse Table 15 Parameter AC Operation Conditions Symbol min. VIH VREF + 0.50 VREF + 0.60 VREF + 0.50 Values typ. max. -- -- -- -- -- -- -- -- -- -- VDDQ + 0.3 VDDQ + 0.3 VDDQ + 0.3 VREF - 0.50 VREF - 0.60 VREF - 0.50 VDDQ + 0.6 VDDQ + 0.6 VDDQ + 0.6 VDDQ + 0.6 V V V V V V V V V V V L3.6, L4.5 -5.0 -3, -3.3, -3.6, -4.5 L3.6, L4.5 -5.0 -3, -3.3, -3.6, -4.5 L4.5 L3.6 -4.5, -5.0 -3, -3.3, -3.6, -4.5 -- -- Unit Notes Input logic high voltage Input logic low voltage VIL VSSQ - 0.3 VSSQ - 0.3 VSSQ - 0.3 Clock Differential Input Voltage (CLK/CLK) VID 1.2 1.0 1.2 1.0 Clock Input Crossing Point (CLK/CLK) I/O Reference Voltage Input Slew Rate VIX VREF VREF - 0.2 1.0 VREF VREF + 0.2 -- -- 0.49 x VDDQ -- 0.51 x VDDQ V rI V/ns -- + Vtt = 0.5xV DDQ 50 Ohm DQ, DQS Test point 15 pF Figure 31 Table 16 Pin Output Test Circuit Pin Capacitances min. 1.0 1.0 max. 2.5 2.5 Unit pF pF A11.. A0, BA1, BA0, CKE, CS, CAS, RAS, WE CLK, CLK Data Sheet 43 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 16 Pin DQ0.. DQ31, DQS0 .. DQS3 DM0.. DM3 Table 17 Interface Parameter Pin Capacitances min. 1.0 1.0 max. 3.0 3.0 Unit pF pF Timing Parameters for speed sorts -3, -3.3, -3.6, -4.5, and -5 -3 MIM -3.3 MIM -3.6 MIM -4.5 WM/MIM -5 WM/MIM Unit Note1) -- 2) Part Number Extension Symbol min. max. min. max. min. max. min. max. min. max. -- -- Clock and Clock Enable Clock Cycle Time System frequency Clock high level width Minimum clock half period tCK tCK fCK fCK tCH 3.0 4.0 200 200 5.0 5.0 333 250 3.3 4.0 200 200 5.0 5.0 300 250 3.6 4.2 200 200 5.0 5.0 278 238 4.5 4.5 183 183 5.5 5.5 222 222 5.0 5.0 183 183 5.5 5.5 200 200 ns ns CL = 4 CL = 3 MHz CL = 4 MHz CL = 3 tCK tCK tCK -- -- -- 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 Clock low level width tCL tHP tCH, tCL -- tCH, tCL -- tCH, tCL -- tCH, tCL -- tCH, tCL -- Command and Address Setup and Hold Times Address and Command input setup time tIS 0.65 -- 0.65 -- 0.75 -- 1.0 -- 1.0 -- ns -- tIH Address and Command input hold time Common Parameters Row Cycle Time Row Cycle Time in Auto Refresh Row Active Time ACTIVE to READ with Auto precharge command Row Precharge Time Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period 0.65 -- 0.65 -- 0.75 -- 1.0 -- 1.0 -- ns -- tRC tRFC tRAS tRAP 39 45 27 -- -- 42.9 -- 49.5 -- 46.8 -- 54 -- 54 63 -- -- 60 70 -- -- ns ns -- -- -- -- 15.7k 29.7 15.7k 32.4 15.7k 36 15.7k 40 15.7k ns ns tRAS (min.)- (burst length * tCK /2) tRP tRRD 12 9.0 -- -- 13.2 -- 9.0 -- 14.4 -- 9.0 -- 18 9.0 -- -- 20 9.0 -- -- ns ns -- -- tCCD 1 6 -- -- 1 6 -- -- 1 6 -- -- 1 6 -- -- 1 6 -- -- tCK tCK -- -- Last data in to Active tDAL (tWR + tRP) Data Sheet 44 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 17 Interface Parameter Timing Parameters for speed sorts -3, -3.3, -3.6, -4.5, and -5 (cont'd) -3 MIM -3.3 MIM -3.6 MIM -4.5 WM/MIM -5 WM/MIM Unit Note1) -- 2) Part Number Extension Symbol min. max. min. max. min. max. min. max. min. max. -- -- Read Cycle Timing Parameters for Data and Data Strobe Data Access Time from Clock DQS edge to Clock edge skew DQS Read Preamble DQS Read Postamble Row to Column Delay Time for Reads tAC tDQSCK tRPRE tRPST tRCDDC -0.5 -0.5 0.7 0.8 4 +0.5 +0.5 0.9 1.1 -- -0.5 -0.5 0.7 0.8 4 +0.5 +0.5 0.9 1.1 -- -0.55 +0.55 -0.7 -0.55 +0.55 -0.7 0.7 0.8 4 0.9 1.1 -- 0.7 0.8 4 +0.7 +0.7 0.9 1.1 -- -0.7 -0.7 0.7 0.8 4 +0.7 +0.7 0.9 1.1 -- ns ns tCK tCK tCK -- -- -- -- -- DQS edge to output tDQSQ data edge skew Data hold skew factor Data Output Hold time from DQS -- -- +0.3 0.33 -- -- +0.3 0.33 -- -- +0.33 -- 0.36 -- +0.45 -- 0.45 -- +0.5 0.5 ns ns ns -- -- -- tQHS tQH tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS Write Cycle Timing Parameters for Data and Data Strobe Row to Column Delay Time for Writes tRCDWR 2 -- 2 -- 2 -- 2 -- 2 -- tCK -- Clock to rising Edge tDQSS DQS (Write Latency) Data-in to DQS Setup Time 0.75 1.1 0.40 -- 0.40 -- 0.75 1.1 0.40 -- 0.40 -- 0.40 -- 0.40 -- 0 -- 0.75 1.1 0.40 -- 0.40 -- 0.40 -- 0.40 -- 0 -- 0.75 1.25 0.6 0.6 0.6 0.6 0 -- -- -- -- -- 0.75 1.25 0.6 0.6 0.6 0.6 0 -- -- -- -- -- tCK ns ns ns ns -- -- -- -- -- -- -- -- tQDQSS Data-in to DQS Hold tQDQSH Time Data Mask to DQS Setup Time Data Mask to DQS Hold Time tDMDQSS 0.40 -- tDMDQSH 0.40 -- 0 -- Clock to DQS Write tWPRES Preamb. Setup Time Clock to DQS Write tWPREH Preamble Hold Time DQS Write Postamble Hold Time Write Recovery Time tCK tCK tCK 0.25 -- 0.4 0.6 0.25 -- 0.4 0.6 0.25 -- 0.4 0.6 0.25 -- 0.4 0.6 0.25 -- 0.4 0.6 tWPST tWR 2 -- 2 -- 2 -- 2 -- 2 -- tCK 3) Data Sheet 45 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 17 Interface Parameter Internal WRITE to READ command delay Write DQS High level Width Timing Parameters for speed sorts -3, -3.3, -3.6, -4.5, and -5 (cont'd) -3 MIM -3.3 MIM -- 1 -- -3.6 MIM 1 -- -4.5 WM/MIM 1 -- -5 WM/MIM 1 -- Unit Note1) -- 2) Part Number Extension Symbol min. max. min. max. min. max. min. max. min. max. -- -- -- tWTR 1 tCK tDQSH 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 tCK tCK -- -- Write DQS Low level tDQSL Width Refresh Cycle Refresh Period (4096 cycles) Average periodic refresh interval Refresh to Refresh command interval tREF tREFC tREFC -- -- -- 32 7.8 15.7 -- -- -- 32 7.8 15.7 -- -- -- 32 7.8 15.7 -- -- -- 32 7.8 15.7 -- -- -- 32 7.8 15.7 ms us s -- -- -- Mode Setup, Power Down & Self Refresh Mode Register Set cycle time Self Refresh Exit time Power Down Exit time tMRD tSREX tPDEX 2 200 -- -- 2 200 -- -- 2 200 -- -- 2 200 -- -- 2 200 -- -- tCK tCK ns -- -- -- 2*tCK -- + tIS 2*tCK -- + tIS 2*tCK -- + tIS 1*tCK -- + tIS 1*tCK -- + tIS 1) All parameters only valid for: TA = 0 to 70 C; VSS = 0 V; 2.5 V < VDD < 2.9 V for -3 and -3.3; 2.375 V < VDD < 2.9 V for -3.6; VDD = 2.5 V 0.125 V for -4.5 and -5; VDDQ = 2.5 V 0.125 V 2) Maximum clock rate is only guaranteed with the specified interface. The SSTL2-Weak Mode interface is limited to a maximum speed of 250MHz. 3) The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS signal. Table 18 Interface Parameter Timing Parameters for speed sorts L3.6 and L4.5 L3.6 MIM Symbol min. max. L4.5 WM/MIM min. max. Unit Note 1) -- -- 2) Part Number Extension -- Clock and Clock Enable Clock Cycle Time System frequency Clock high level width Data Sheet 3.6 6.0 10 278 238 0.55 4.5 4.5 166 100 0.45 6.0 10 222 222 0.55 ns ns CL = 4 CL = 3 tCK fCK fCK tCH 46 4.2 166 100 0.45 MHz CL = 4 MHz CL = 3 tCK -- V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 18 Interface Parameter Clock low level width Minimum clock half period Command and Address Setup and Hold Times Address and Command input setup time Address and Command input hold time Common Parameters Row Cycle Time Row Cycle Time in Auto Refresh Row Active Time ACTIVE to READ with Auto precharge command Row Precharge Time Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period Last data in to Active (tWR + tRP) Timing Parameters for speed sorts L3.6 and L4.5 (cont'd) L3.6 MIM Symbol min. max. 0.55 -- L4.5 WM/MIM min. 0.45 max. 0.55 -- Unit Note 1) -- -- 2) Part Number Extension -- -- -- tCL tHP 0.45 tCH, tCL tCH, tCL tCK tCK tIS tIH 0.75 0.75 -- -- 1.0 1.0 -- -- ns ns -- -- tRC tRFC tRAS tRAP tRP tRRD tCCD tDAL 46.8 54 32.4 14.4 9.0 1 6 -- -- 54 63 -- -- ns ns ns -- -- -- -- -- -- -- -- 15.7k 36 -- -- -- -- 18 9.0 1 6 15.7k ns -- -- -- -- ns ns tRAS (min.)- (burst length * tCK /2) tCK tCK Read Cycle Timing Parameters for Data and Data Strobe Data Access Time from Clock DQS edge to Clock edge skew DQS Read Preamble DQS Read Postamble Row to Column Delay Time for Reads DQS edge to output data edge skew Data hold skew factor Data Output Hold time from DQS tAC tDQSCK tRPRE tRPST tRCDDC tDQSQ tQHS tQH -0.55 -0.55 0.7 0.8 4 -- -- +0.55 -0.7 +0.55 -0.7 0.9 1.1 -- 0.36 0.7 0.8 4 -- +0.7 +0.7 0.9 1.1 -- 0.45 ns ns -- -- -- -- -- -- -- -- tCK tCK tCK ns ns +0.33 -- +0.45 ns tHP - tQHS tHP - tQHS Write Cycle Timing Parameters for Data and Data Strobe Row to Column Delay Time for Writes Clock to rising Edge DQS (Write Latency) Data-in to DQS Setup Time Data-in to DQS Hold Time Data Mask to DQS Setup Time Data Mask to DQS Hold Time Clock to DQS Write Preamb. Setup Time Clock to DQS Write Preamble Hold Time DQS Write Postamble Hold Time Write Recovery Time Data Sheet tRCDWR tDQSS tQDQSS tQDQSH tDMDQSS tDMDQSH tWPRES tWPREH tWPST tWR 47 2 0.75 0.40 0.40 0.40 0.40 0 0.25 0.4 2 -- 1.1 -- -- -- -- -- -- 0.6 -- 2 0.75 0.6 0.6 0.6 0.6 0 0.25 0.4 2 -- 1.25 -- -- -- -- -- -- 0.6 -- tCK tCK ns ns ns ns -- -- -- -- -- -- -- -- -- 3) tCK tCK tCK tCK V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 18 Interface Parameter Internal WRITE to READ command delay Write DQS High level Width Write DQS Low level Width Refresh Cycle Refresh Period (4096 cycles) Average periodic refresh interval Refresh to Refresh command interval Mode Setup, Power Down & Self Refresh Mode Register Set cycle time Self Refresh Exit time Power Down Exit time Timing Parameters for speed sorts L3.6 and L4.5 (cont'd) L3.6 MIM Symbol min. max. -- 0.65 0.65 L4.5 WM/MIM min. 1 0.35 0.35 max. -- 0.65 0.65 Unit Note 1) -- -- 2) Part Number Extension -- -- -- -- tWTR tDQSH tDQSL 1 0.35 0.35 tCK tCK tCK tREF tREFC tREFC -- -- -- 32 7.8 15.7 -- -- -- 32 7.8 15.7 ms us us -- -- -- tMRD tSREX tPDEX 2 200 -- -- 2 200 -- -- tCK tCK ns -- -- -- 2*tCK+tIS -- 1*tCK+tIS -- 1) All parameters only valid for: TA = 0 to 70 C; VSS = 0 V; 2.375 V < VDD < 2.9 V for L3.6; VDD = 2.5 V 0.125 V for L4.5; VDDQ = 2.5 V 0.125 V 2) Maximum clock rate is only guaranteed with the specified interface. The SSTL2-Weak Mode interface is limited to a maximum speed of 250MHz. 3) The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS signal. Table 19 HYB25D128323C-3 CAS latency 4 4 4 3 3 3 Frequency / tCK 333 MHz / 3.0 ns 300 MHz / 3.3 ns 278 MHz / 3.6 ns 250 MHz / 4.0 ns 222 MHz / 4.5 ns 200 MHz / 5.0 ns tRC 13 13 13 12 10 9 tRFC 15 15 15 14 12 11 tRAS 9 9 9 8 7 6 tRP 4 4 4 4 3 3 tWR 2 2 2 2 2 2 tRRD 3 3 3 3 2 2 tDAL 6 6 6 6 5 5 tRCDRD 4 4 4 3 3 3 tRCDWR 2 2 2 2 2 2 Units tCK tCK tCK tCK tCK tCK Data Sheet 48 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 20 HYB25D128323C-3.3 CAS latency 4 4 3 3 3 Frequency / tCK 300 MHz / 3.3 ns 278 MHz / 3.6 ns 250 MHz / 4.0 ns 222 MHz / 4.5 ns 200 MHz / 5.0 ns tRC 13 13 12 10 9 tRFC 15 15 14 12 11 tRAS 9 9 8 7 6 tRP 4 4 4 3 3 tWR 2 2 2 2 2 tRRD 3 3 3 2 2 tDAL 6 6 6 5 5 tRCDRD 4 4 3 3 3 tRCDWR 2 2 2 2 2 Units tCK tCK tCK tCK tCK Table 21 HYB25D128323C-3.6 CAS latency 4 4 3 3 Frequency / tCK 278 MHz / 3.6 ns 250 MHz / 4.0 ns 222 MHz / 4.5 ns 200 MHz / 5.0 ns tRC tRFC 13 13 12 10 15 15 14 12 tRAS 9 9 8 7 tRP 4 4 4 3 tWR 2 2 2 2 tRRD 3 3 2 2 tDAL 6 6 6 5 tRCDRD 4 4 4 3 tRCDWR 2 2 2 2 Units tCK tCK tCK tCK Table 22 HYB25D128323C-4.5 CAS latency 3 3 3 Frequency / tCK 222 MHz / 4.5 ns 200 MHz / 5.0 ns 183 MHz / 5.5 ns tRC tRFC 12 12 12 14 14 14 tRAS 8 8 8 tRP 4 4 4 tWR 2 2 2 tRRD 2 2 2 tDAL 6 6 6 tRCDRD 4 4 4 tRCDWR 2 2 2 Units tCK tCK tCK Table 23 HYB25D128323C-5 CAS latency 3 3 Frequency / tCK 200 MHz / 5.0 ns 183 MHz / 5.5 ns tRC tRFC 12 12 14 14 tRAS 8 8 tRP 4 4 tWR 2 2 tRRD 2 2 tDAL 6 6 tRCDRD 4 4 tRCDWR 2 2 Units tCK tCK Data Sheet 49 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 24 HYB25D128323CL3.6 CAS latency 4 4 3 3 3 Frequency / tCK 278 MHz / 3.6 ns 250 MHz / 4.0 ns 222 MHz / 4.5 ns 200 MHz / 5.0 ns 166 MHz / 6.0 ns tRC tRFC 13 13 12 10 9 15 15 14 12 11 tRAS 9 9 8 7 6 tRP 4 4 4 3 3 tWR 2 2 2 2 2 tRRD 3 3 2 2 2 tDAL 6 6 6 5 5 tRCDRD 4 4 4 3 3 tRCDWR 2 2 2 2 2 Units tCK tCK tCK tCK tCK Table 25 HYB25D128323CL4.5 CAS latency 3 3 3 3 3 Frequency / tCK 222 MHz / 4.5 ns 200 MHz / 5.0 ns 183 MHz / 5.5 ns 166 MHz / 6.0 ns 143 MHz / 7.0 ns tRC tRFC 12 12 12 10 9 14 14 14 12 11 tRAS 8 8 8 7 6 tRP 4 4 4 3 3 tWR 2 2 2 2 2 tRRD 2 2 2 2 2 tDAL 6 6 6 5 5 tRCDRD 4 4 4 3 3 tRCDWR 2 2 2 2 2 Units tCK tCK tCK tCK tCK Table 26 Operating Currents Symbol -3 max. 200 -3.3 -3.6 -4.5 -5.0 L3.6 L4.5 Unit Notes typ. 190 180 160 150 typ. mA 1) Parameter & Test Condition OPERATING CURRENT: One bank; IDD0 Active-Precharge; tRC = tRC(min.); tCK = tCK(min.); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; IDD1 Active-Read-Precharge; BL=4; CL=4; tRCDDC = 4*tCK; tRC = tRC(min.); tCK = tCK(min.); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN IDD2P STANDBY CURRENT: All banks idle; power-down mode; tCK = tCK(min.); CKE=LOW 230 220 110 190 180 mA 26 22 22 14 14 10 7 mA Data Sheet 50 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Electrical Characteristics Table 26 Operating Currents (cont'd) Symbol -3 max. IDLE STANDBY CURRENT: CKE=HIGH; CS#=HIGH (DESELECT); All banks idle; tCK = tCK(min.); Address and control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM 130 -3.3 -3.6 -4.5 -5.0 L3.6 L4.5 Unit Notes typ. 120 110 100 100 typ. mA Parameter & Test Condition IDD2F ACTIVE POWER-DOWN STANDBY IDD3P CURRENT: one bank active; powerdown mode; CKE=LOW; tCK = tCK(min.); ACTIVE STANDBY CURRENT: CS#=HIGH; CKE=HIGH; one bank active; tRC = tRC(max.); tCK = tCK(min.); Address and control inputs changing once per clock cycle; DQ, DQS, and DM inputs changing twice per clock cycle 65 60 55 50 50 mA IDD3N 130 120 110 100 100 mA OPERATING CURRENT BURST IDD4R READ: BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK = tCK(min.); Iout=0mA; 50% of data changing on every transfer OPERATING CURRENT BURST IDD4W WRITE: BL=2; WRITES; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK = tCK(min.); DQ, DQS, and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT: tRC = tRFC(min.); tCK = tCK(min.) SELF REFRESH CURRENT: Self Refresh Mode; CKE<=0.2V; tCK = tCK(min.) 370 350 330 290 280 190 160 mA 370 350 330 290 280 200 175 mA IDD5 IDD6 320 20 300 16 280 16 240 10 230 10 4 3 mA mA IDD7 BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4; with Auto Precharge; tRC = tRC(min.); tCK = tCK(min.); Address and control inputs change only during Active, READ, or WRITE commands 1) Measured with output open. 430 400 370 320 300 mA 1) Data Sheet 51 V1.7, 2003-07 HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5] 128 Mbit DDR SGRAM [4M x 32] Package Outlines 5 Package Outlines Module Package The package is conforming with JEDEC MO-205 Variation BD General Tolerances according to ISO 8015 The inner matrix of 4 x 4 balls is reserved for thermal contacts 11.1 10.9 11.1 10.9 1.50 1.44 1.36 -0.85 0.8 -- 0.10 8.8 8.8 0.8 -- 8.8 8.8 MAX All dimensions in mm. Notation is TYP or MAX or TYP MIN MIN Figure 32 Package Outlines Data Sheet 52 V1.7, 2003-07 www.infineon.com Published by Infineon Technologies AG |
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